1. Technical Field
The present invention relates to an N-digit subtraction unit, an N-digit subtraction module, an N-digit addition unit and an N-digit addition module.
2. Related Art
An operator such as an adder and a subtracter, which are basic devices for arithmetic operation, has been designed in various ways depending on its use (Kai Hwang: “Computer Arithmetic-PRINCIPLES, ARCHITECTURE AND DESIGN”, John Wiley & Sons, Inc (1979): Non-Patent Document 1). For example, a carry propagation scheme has been most commonly used for arithmetic operation. In this scheme, since carry is propagated among digits, a propagation delay and the number (area) of gates are in proportion to digits (Tsugio Nakamura, “Basis of Digital Circuit”, NRS, 1992: Non-Patent Document 2).
A redundant binary representation method, which provides the highest-speed for arithmetic operation, requires a number of gates since one digit is represented by two bits (Tsugio Nakamura, Kazuhiro Abe, Narito Fuyutsume, Hiroshi Kasahara, and Teruo Tanaka: “Super-high Speed, Accuracy, and Modularized Residue Number System based on Redundant Binary Representation”, IEEJ Trans.EIS, Vol. 125, No. 6, pp. 879-886 (2005): Non-Patent Document 3)(Yoshitaka Tsunekawa, Mitsuki Hinosugi, Masato Saito, Katsumi Abukawa, and Mamoru Miura: “High-Performance Redundant Binary Adder Representing Each Digit by Hybrid 2 Bits/3 Bits and Its Application to Multiplier”, T.IEE Japan, Vol. 119-C, No. 5, pp. 644-653 (1999): Non-Patent Document 4). A lookahead carry scheme allows relatively high-speed processing since it performs a carry/borrow operation in addition to an adding operation, but this scheme is not suitable for increase of area and distributed processing for the increased number of digits. In addition, there is a Non-Patent Document disclosing a conventional technique, authored by Yoshitaka Tsunekawa, Mitsuki Hinosugi, Masato Saito, Katsumi Abukawa, and Mamoru Miura, “High-Performance Redundant Binary Adder Representing Each Digit by Hybrid 2 Bits/3 Bits and Its Application to Multiplier”, T.IEE Japan, Vol. 119-C, No. 5, pp. 644-653 (1999).